On-chip busses (OCB) are now commonly found in field programmable gate arrays (FPGA) and other system-on-a-chip (SoC) devices. An address-based OCB allows software or an FPGA master to read or write anywhere to an FPGA slave. However, current OCB architecture does not work in system environments including more than one FPGA on a chip, or across multiple chips. One solution involves an individual control bus for each FPGA in the system, where each FPGA is marked as a different logical destination. However, such a “chip to chip” architecture is not easily modified, as software must be changed with each modification to ensure that data reaches the intended physical device. In addition, only a single off-chip destination is allowed, and the “chip to chip” solution does not provide for burst support, bidirectionality, or full duplex communications.